Access control for plural magnetic memories

ABSTRACT

An access control system for handling a plurality of types of addressable-memory systems is described. Memory devices of varying types and having varying addressing systems are controlled and can be coupled to a single data processor input/output channel. The access control system described includes circuitry for responding to selected fields of control words for establishing the length and bit positions of other control fields in the control words.

United States Patent [72] Inventor Anthony R. Talarczyk Bloomlngton,Min. [21] Appl. No. 756,830 [22] Filed Sept. 3, 1968 [45] Patented Mar.2, 1971 [73] Assignee Sperry Rand Corporation New York, N.Y.

[54] ACCESS CONTROL FOR PLURAL MAGNETIC MEMORIES 8 Claims, 38 DrawingFigs.

[ 52] US. Cl 340/1725 [51] Int.Cl G06f13/00 [50] Fieldol'Seamh 235/157;340/172.5

[56] References Cited UNITED STATES PATENTS 3,230,513 1/1966 Lewis340/1725 3,2 1,862 1/1966 Blosk et a1. 340/1725 3,292,151 12/1966 Barneset a1. i. 340/1725 3,317,902 5/1967 Michael .1 340/172.5 3.343,1409/1967 Richmond et a1... .1 340/l72.5 3,432,810 3/1969 Cordero 340/17253,437,998 4/1969 Bennett et a1 340/1725 3,469,241 9/1969 Barton et a].340/1725 Primary Examiner-Gareth D. Shaw Assistant Examiner Melvin B.Chapnick Attorneys-Thomas J Nikolai, Kenneth G. Grace and John P.

Dority PROCESSOR 1O r (5 PROCESSOR 24 2 ACCESS CONTROL n /1512 UNIT OPROCESSOR 22 PATENTEUHAR 2197i 3,568,160

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FROM DRUMS INVENTOR ANTHONY R. TALARCZYK BY AT ORNEY PATENTEDHAR 2m3568.160

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' PROCESSOR PROCESSOR ACCESS 24 MAGNETIC 2 CONTROL DRUMS UNIT 'PROCESSOR Fig. 3

TYPE DRUM OPTION CODE TYPE ADDRESS ALLOCATION I P=O 11 O 7,T77,777

P= l- 7 I 10,000,000 77, 717,771 2 P=06 I O 67,777,77|

3 P=O? 1 O- 77,777,777

. TYPE I CAPACITY=2,097,I52 WORDS TYPE 11 CAPACITY=262,I44 WORDSPATENTEDMAR 21911 3.558; 160

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PATENTEU HAR 215m SHEET 09 0F 2 3,568,160

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1. A data processing system comprising: a plurality of memory devices ofat least two distinct types having addressable storage locations thereonand unique addressing signal formats; access control means coupledintermediate said plurality of memory devices and said programmable dataprocessing means including register means for at least temporarilystoring addressing signals to either a first or a second format; memorydevice type decoding means coupled to a portion of said register meansfor providing memory type output signals indicative of the type of saidmemory device selected; memory device type decoding means coupled to aportion of said register means for providing memory type output signalsindicative of the type of said memory device selected; memory deviceselection means coupled to said memory device type decoding means and tosaid register means for determining the one of said plurality of memorydevices to be accessed; and address selecting means adapted to receivesaid type output signals and coupled to said register means forgenerating addressing signals unique to the type of memory deviceselected by said memory device selection means.
 2. A data processingsystem as in claim 1 wherein said memory device type decoding meansincludes option selection means for selecting one of a plurality ofoptions of address sequences for said plurality of memory devices.
 3. adata processing system as in claim 1 wherein said plurality of memorydevices includes at least first and second types of magnetic drum memorysystems each of said types having different addressable memorycapacities requiring said unique addressing signals, said uniqueaddressing signals including a designation of an angular addressposition for defining the position around the periphery of said magneticdrum memory systems and the band position along said magnetic drummemory system, said angular address position and said band positiondesignations requiring different addressing signal combinations for eachof said types.
 4. Access control means for use intermediate at least oneprogrammable data processor and a plurality of addressable memorysystems including at least two distinct types of rotating magneticmemory devices, any one of which can be coupled to a processorinput/output channel, each of said rotating magnetic memory deviceshaving angular address signals recorded therein for indicating thepresent positions of the rotating magnetic memory devices and datasignals recorded in circumferential bands on the magnetizable surfacethereof wherein said access control means includes: first input meansfor receiving control words from the data processor, said control wordscomprised of a first plurality of control signals indicative of theprogrammably selected one of the types of the addressable memory systemsto be coupled to the input/output channel, and a second plurality ofcontrol signals indicative of the desired addressable location in saidaddressable memory system, said second plurality of control signalsincluding a first group of signals indicative of an angular address anda second group of signals indicative of a desired band; register meanshaving a plurality of stages coupled to said first input means for atleast temporarily storing said control words; memory system type enablemeans coupled to a first predetermined number of said plurality ofstages of said register means for providing memory system type enablesignals indicative of the type of said addressable memory systemindicated by said first plurality of control signals; memory systemselect means coupled to a second predetermined number of said pluralityof stages and to said memory system type enable means for selecting aspecified one of said plurality of addressable memory systems; aDdressselect and driver means coupled to a third predetermined number of saidplurality of stages and to said memory system type enable means forselecting a specified band in response to said second group of signals;second input means coupled to the plurality of addressable memorysystems for receiving angular address signals from the one of saidmemory systems selected; angular address register means coupled to saidsecond input means and to said memory system type enable means forreceiving and at least temporarily storing angular addresses from saidmemory system selected; comparator means coupled to said angular addressregister means, said memory system type enable means, and a fourthpredetermined number of said plurality of stages for providing acoincidence signal when the angular address read from said memory systemselected has a predetermined relationship to said first group of signalsindicative of the angular address to be accessed; and said second,third, and fourth predetermined numbers of said plurality of stagesdependent on said memory system type enable signals.
 5. An accesscontrol means as in claim 4 wherein said memory system type enable meansincludes switchable option selection means for selecting one of aplurality of options of address sequences for said plurality of memorysystems.
 6. For use in a data processing system having at least oneprogrammable data processor and at least two types of memory systems forstoring data at addressable locations therein, an access control devicefor permitting the processor by programmable selection to communicatewith selected ones of said types of addressable memory systems over asingle input/output channel, said access control device comprising:input means for receiving control words from the programmable dataprocessor comprised of a first plurality of programmably alterablecontrol signals indicative of one of said two types of addressablememory system selected and a second plurality of programmably alterablecontrol signals indicative of a desired addressable location; memorysystem type enable means coupled to said input means for interpretingsaid first plurality of control signals for providing memory system typeenable signals indicative of the type of said addressable memory systemselected; and address select means coupled to said input means and saidmemory type enable means for selecting the required effectivesignificance of ones of said second plurality of control signals inresponse to respective ones of said memory system type enable signalsfor accessing the selected one of said types of addressable memorysystems for accommodating the different addressing signal requirementsof each of said types of addressable memory systems.
 7. An accesscontrol device as in claim 6 wherein said memory system type enablemeans includes switchable option selection means for selecting one of aplurality of options of address sequences for said plurality of memorysystems.
 8. An access control device as in claim 7 wherein said optionselection means includes means for selecting one of said options whereinonly one of said types of addressable memory systems will be accessed.